1. Field of the Invention
The present invention relates to electronics components and, in particular, to a process for producing integrated electronic capacitors and resistors.
2. Description of Related Art
Common parallel plate capacitors have two spaced parallel conducting plates separated by a dielectric. The capacitance is a function of the area of the plates and the thickness of the dielectric between the plates. This relationship is defined by the equation C=.epsilon.A/d where C is capacitance, .epsilon. is the permittivity of the dielectric, A is the area and d is the plate separation or dielectric thickness. As a function of the equation, and without changing the dielectric, the capacitance can be increased by increasing the area of the plates or by decreasing the dielectric thickness.
Microelectronic components and packages are small in area and technology is driving them to be smaller and smaller; therefore, increasing the size of the plates is not a favorable option when seeking to increase the capacitance of a package or component. Decreasing the thickness of the dielectric between the plates is a favorable way to increase the capacitance while decreasing the size of the package. Also, the capacitance can be increased by configuring multiple capacitors in parallel.
Ceramic capacitors are produced for component packages by processes which include layering alternating thin conductors which form electrodes, and unfired ceramics slayers called greensheets (nominally 0.2 mm to 0.28 mm thick) which form the dielectrics. Processes such as metal mask extrusion printing, silk screen printing and tape casting are used to produce the capacitors. Typically, as illustrated in the exploded view of FIG. 1a, conductive layers 16 are formed adjacent to greensheet layers 14 and an additional greensheet 15 of the same area as greensheet 14 forms the dielectric layer between the conductive layers. Alternately, multiple capacitors may be layered within the package. The capacitors formed by these methods are thick, and the dielectric layer 15 resides on the entire surface of the greensheet layers 14.
Other processes which are directed at manufacturing multilayer capacitors include U.S. Pat. No. 3,235,939, U.S. Pat. No. 4,347,650 and U.S. Pat. No. 4,586,972 which disclose methods of making discrete capacitors which can not be integrated into a ceramic package.
A capacitor component with multiple parallel capacitors can be formed to attain increased capacitance. The capacitance of parallel capacitors adds such that the total capacitance of multiple capacitors is the sum of the capacitance of each individual capacitor. Thus, capacitors in a component can be stacked and interconnected in order to increase the total capacitance of a component. The interconnection of the capacitors is important in the resulting component. Available interconnections methods do not provide interconnection flexibility of the components. FIG. 1b is a cross-sectional view of a discrete surface mount multilayer capacitor. The ceramic greensheets 44 form dielectrics, and electrodes 40 terminate at end terminals 42. The termination is not flexible and all of the capacitors of the discrete component are connected in parallel. Patternable electrodes would allow the termination flexibility necessary for interconnecting capacitors in packages in various configurations. However the aforementioned methods do not produce patterned electrode layers.
Metal mask extrusion printing and silk screen printing can produce patterned layers of conductive or dielectric materials of thicknesses from 0.6 to 2.5 mils on greensheets. Tape casting can produce greensheets as thin as 2 to 3 mils. The tape cast layers require patterned metallization deposition and require repeated handling of the flexible greensheets which introduces distortion to the greensheets. Metallization printing also causes greensheet distortion due to the interaction of the ink solvent and the greensheet organic binder. In addition, multiple oven dryings are required causing further distortion damage to the greensheets.
One approach to the patterning problem is U.S. Pat. No. 3,235,939 which discloses capacitors made from tape casted ceramic with a metallic material applied thereon. The tape cast ceramic is thick. A hole is formed in the ceramic by drilling or punching and the capacitor is fired prior to the introduction of a central solder conductor into the hole. The result is a thick discrete capacitor component with all of the stacked multiple capacitors connected in connected in parallel. Thus, the method does not provide interconnection flexibility.
Another aspect of multiple printings of thick layers of dielectric and conductors in a patterned area is the unwanted distortion that is created on the exterior surfaces of the electronic package. An area of great thickness inside the package will create a bump or bulge on the surface due to uneven unfired densities. This can cause problems with attachment of surface mount components such as integrated circuits, resistors, pins, etc. The multiple layers deposited inside the electronic package should be as thin as possible in order to maximize the surface planarity. In addition to having very thin dielectric layers to maximize the capacitance it is imperative that the dielectric layer be pinhole free so as to prevent the metallization above and below the dielectric from shorting together.
The formation of an integrated resistor is also desirable, singularly or in combination with other resistors and capacitors. Thin resistive layers of, for example, a cermet, which is a mixture of ceramic and metal, can not be formed thinly enough by the above mentioned processes to be integrated into a package.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a process for making integrated capacitors whereby the capacitors can be created within or on the ceramic package.
It is another object of the present invention to provide a process, for applying layers to a substrate, which has rapid drying time and which does not require oven drying.
It is another object of the present invention to provide thin pinhole free layers.
A further object of the invention is to provide a process for applying layers to a substrate minimizing distortion of the substrate.
It is yet another object of the present invention to provide thin patternable layers with interconnection flexibility.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.